From bba9f7df211d63293e2a957872d156a0a6dfcd48 Mon Sep 17 00:00:00 2001 From: Marcel Ribeiro-Dantas Date: Sat, 10 Dec 2022 12:05:34 -0300 Subject: Fixes typos in many different English articles Signed-off-by: Marcel Ribeiro-Dantas --- hdl.html.markdown | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'hdl.html.markdown') diff --git a/hdl.html.markdown b/hdl.html.markdown index 3c3aff66..6b9a2d80 100644 --- a/hdl.html.markdown +++ b/hdl.html.markdown @@ -12,7 +12,7 @@ It is used by circuit designers to simulate circuits and logic prior to wiring a HDL allows circuit designers to simulate circuits at a high level without being connected to specific components. ## Basic building blocks & introduction to the language--- -This programming language is built by simulating hardware chips and wiring. Normal programming functions are replaced with specialized chips that are added to the current wiring desing. Every base chip must be written as it's own file and imported to be used in the current chip, though they may be reused as often as desired. +This programming language is built by simulating hardware chips and wiring. Normal programming functions are replaced with specialized chips that are added to the current wiring design. Every base chip must be written as it's own file and imported to be used in the current chip, though they may be reused as often as desired. ```verilog // Single line comments start with two forward slashes. @@ -79,7 +79,7 @@ foo(in=a[0..7], out=c); // C is now a 2 bit internal bus // Note that internally defined busses cannot be subbussed! -// To access these elements, output or input them seperately: +// To access these elements, output or input them separately: foo(in[0]=false, in[1..7]=a[0..6], out[0]=out1, out[1]=out2); // out1 and out2 can then be passed into other circuits within the design. -- cgit v1.2.3